SENIOR PHYSICAL DESIGN ENGINEER - CORK CITY- IRELAND

Client:

Our client a leading Multinational Semiconductor Wireless Organisation requires a Senior Physical Design Engineer role based in Cork City, Ireland.

Role:

You will be part of a global team that will drive and execute on all phases of the complete physical design flow for the next generation of SOCs in bleeding edge technologies.

You will be part of a world-wide team responsible for the complete Physical Implementation and Sign-off for the next-gen cores in chips.

Responsibilities:

• Working on the physical design execution from floorplan to GDS for high-speed complex designs with aggressive PPA targets.
• Managing schedules, plans, status, risks and support cross-functional engineering effort.
• Working with design and DFT teams on understanding design in context of physical design timing closure and power optimization
• Demonstrating good understanding of and conducts research on industry trends and innovations in physical design to ensure solutions and deliverables align with best practices.
• Conducting complex analyses of test results using statistics and data predictions to track benchmarks and identify issues or areas for improvement.
• Working across teams to align on important areas of PPA improvement and ensure targets are met; ensures designs are innovative and compatible with highest standards.
• Taking part in the research of innovative methodologies for pushing the PPA limits in physical design, including the development of new scripts and flows.

Education:

Bachelor's Degree in Electronic Engineer or equivalent
 

Experience:

• 3+ years of relevant experience in Physical Design.
• Knowledge of entire PD flow from netlist to GDS (Floorplanning, Power planning, Placement/CTS/Routing and corresponding optimization steps).
• Good experience and knowledge of tools for physical design implementation in advanced technologies nodes (10nm and below).
• Experience using different techniques for low power designs and UPF/CPF flows and understanding of Conformal Low Power (CLP).
• Excellent understanding of STA and timing closure methodologies, including effect on congestion/routing/power.
• Understanding of power analysis and power integrity analysis.
• Understanding of Physical Verification and DRC closure.
• Expert in automation skills using Perl and tcl and able to develop/support flows related to physical design.
• Good communication skills and ability & desire to work in a cross-functional team environment